The present invention relates to a high-power vertical semiconductor device and, more particularly, to a semiconductor device having a super-junction layer as part of a semiconductor substrate.
To miniaturize and enhance the performance of power source apparatus in the power electronics field, power semiconductor devices are required to be reduced in loss and increased in breakdown resistance and operation speed as well as increased in breakdown voltage and current capacity. To satisfy these requirements, the super-junction substrate has been proposed as a substrate structure of a semiconductor device and the vertical MOS power device structure has been proposed as a surface structure.
For purposes of this discussion, the terms “n-type semiconductor” and “p-type semiconductor” mean semiconductors having electrons and holes, respectively, as majority carriers. The marks “+” and “−” of n+, n−, etc. will refer to the impurity concentration of the semiconductor concerned is higher and lower, respectively, than that of a semiconductor that is not given either of those marks.
The semiconductor substrate having a single conductivity type and the super-junction substrate are commonly known substrate structures of a semiconductor device. The super-junction substrate has, between a first conductivity type semiconductor substrate and a second conductivity type semiconductor layer, a super-junction layer in which first conductivity type semiconductor layers and second conductivity type semiconductor layers are formed alternately in the direction that is perpendicular to the semiconductor substrate (refer to U.S. Pat. No. 6,097,063 (JP-A-9-266311) and U.S. Pat. No. 6,888,195 B2 (JP-A-2004-119611), for example). In the super-junction substrate, a space charge region can develop to occupy the super-junction layer in an off period even in the case where concentration of each of the layers constituting the super-junction layer is high. Therefore, the on-resistance of a high-breakdown-voltage semiconductor device, in particular, can be reduced.
The planar structure in which a gate electrode is formed on a semiconductor substrate and the trench structure in which gate electrodes are buried in trenches of a semiconductor substrate are commonly known surface structures of a semiconductor device. Trench MOS devices have a trench gate structure in which many trench MOS cells having trench side walls as channel regions are provided in a semiconductor substrate. In general, trench MOS devices are easier to improve in performance than planar MOS devices by reducing the channel resistance. In recent years, as for vertical devices, vertical MOS devices having the trench structure have been proposed because they are easier to attain a low-on-resistance characteristic by virtue of their structure (refer to JP-A-4-233765, U.S. Pat. No. 5,304,821A (JP-A-146674), and JP-A-5-335582, for example).
An example of such vertical MOS devices will be described below. FIG. 25 is a sectional view showing the structure of a conventional vertical MOS device. As shown in FIG. 25, this conventional vertical MOS device is manufactured by using a semiconductor substrate in which an n+ drain layer 30, an n− drain layer 31, and a p− channel region 32 are laid one on another in this order. Many trenches 33 penetrate through the p− channel region 32 so as to reach the n− drain layer 31. Gate electrodes 35 made of polysilicon or the like are formed on the surfaces of the trenches 33 with gate oxide films 34 interposed in between, respectively. P+ body regions 37 are formed on the surface of the p− channel region 32 approximately at the centers between the trenches 33. And n++ source regions 36 are formed so as to be in contact with the p+ body regions 37 and the trenches 33. A metal electrode 39 made of aluminum or the like is formed on the gate electrodes 35 with an insulating layer 38 interposed in between. The metal electrode 39 is in ohmic contact with the p+ body regions 37 and the n++ source regions 36.
In this vertical MOSFET, when a voltage that is higher than a prescribed threshold voltage is applied to the gate electrodes 35, n-type inversion layers are formed in the p− channel region 32 parallel with the trenches 33 and current paths are formed between the n++source regions 36 and the drain layers 31 and 30. As a result, a conductive state is established between the source and the drain of the vertical MOSFET. When the voltage of the gate electrodes 35 is made lower than the threshold voltage, the n-type inversion layers in the p− channel region 32 disappear and a cutoff state is established between the source and the drain of the vertical MOSFET. In vertical MOSFETs, since as described above vertical current paths are formed parallel with the trenches 33, the current path length (in the n− drain layer 31) can be made much shorter and hence the on-resistance can be made lower than in planar MOSFETs.
Vertical MOSFETs, however, have a problem that the device is destroyed if a high voltage is applied between the source and the drain in a gate off state and avalanche current starts to flow. As a result, the device is prone to be destroyed also when it is turned off from a current conduction state. This is a major obstruction to expansion of uses.
FIG. 26 is a sectional view of part of a conventional super-junction substrate and shows its structure. That is, FIG. 26 shows part of a super-junction substrate that is cut out along lines C-C′ and D-D′ and the super-junction substrate is such that the structures each shown in FIG. 26 are arranged in the right-left direction. FIG. 27 is a graph showing an electric field profile along the cutting line C-C′ in FIG. 26. In a vertical MOSFET using this super-junction substrate, when a high voltage is applied between the source and the drain, a depletion layer develops over the entire super-junction region and a voltage is held there. In this case, an approximately rectangular electric field profile is obtained as indicated by a solid line in FIG. 27. When avalanche current starts to flow, the current profile changes to one indicated by a broken line. It is seen that the voltage held which is an electric field integration value is made smaller. This is a negative resistance characteristic and is considered due to the structure of the super-junction substrate. As a result, current is concentrated in part of the device and the device is destroyed.
A semiconductor device capable of securing a high device breakdown voltage has been proposed in which the pn repetition pitch of a parallel pn structure in an inactive area is set smaller than that of a parallel pn structure in an active area on a first major surface side in which a device surface structure is formed and is set the same as that of the latter on a second major surface side (refer to JP-A-2005-51190, for example). In this semiconductor device, a depletion layer is apt to develop and reduction in breakdown voltage due to charge imbalance can be suppressed. As a result, a sufficiently high breakdown voltage can be secured in a well-balanced manner in the entire device.
In the technique disclosed in JP-A-2005-51190, however, a problem remains that the device is destroyed when large current such as avalanche current flows. The complex structure that the pn repetition pitch of the parallel pn structure in the inactive region on the first major surface side needs to be set different from that on the second major surface side leads to another problem that manufacture of a super-junction substrate takes extra time and work.